Chip design for submicron VLSI : CMOS layout and simulation (Record no. 12448)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00619nam a22001457a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9788131501955 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 UYE |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Uyemura, John P. (John Paul), |
| 245 ## - TITLE STATEMENT | |
| Title | Chip design for submicron VLSI : CMOS layout and simulation |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi, India |
| Name of publisher, distributor, etc. | Cengage Learning |
| Date of publication, distribution, etc. | 2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xvi, 411 p. |
| Other physical details | ill. ; |
| Accompanying material | 1 CD-ROM (4 3/4 in.) |
| 500 ## - GENERAL NOTE | |
| General note | Includes bibliographical references and index. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | 1. Microwind. 2. Metal oxide semiconductors, Complementary --Design and construction. 3. Integrated circuits --Very large scale integration --Design and construction. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Book |
| Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library (CL) | Central Library (CL) | General Stacks | 12/27/2013 | Saeed Book Bank | 741.20 | 621.395 UYE | SEECS012827 | 01/01/2014 | 01/01/2014 | Book |