Advanced digital design with Verilog HDL / (Record no. 190277)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01397 a2200253 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | Nust |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20221006102302.0 |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER | |
| LC control number | 2002074816 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0-13-089161-4 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (DLC) 2002074816 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | Nust |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395,CIL |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Ciletti, Michael D. |
| 9 (RLIN) | 52068 |
| 245 10 - TITLE STATEMENT | |
| Title | Advanced digital design with Verilog HDL / |
| Statement of responsibility, etc. | Michael Ciletti. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Upper Saddle River, NJ : |
| Name of publisher, distributor, etc. | Pearson Education, |
| Date of publication, distribution, etc. | cop. 2003. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 982 p. : |
| Other physical details | ill. |
| 440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE | |
| Title | Prentice Hall Xilinx design series |
| 9 (RLIN) | 3114 |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Introduction to digital design methodology (Page-1), Review of combinational logic design (Page-13), Fundamentals of sequential logic design (Page-69), Introduction to logic design with verilog (Page-103), Logic design with behavioral models of combinational and sequential logic (Page-143), Synthesis of combinational and sequential logic (Page-233), Design and synthesis of datapath controllers (Page-347), Programmable logic and storage devices (Page-415), Algorithms and architectures for digital processors (Page-547), Architectures for arithmetic processors (Page-651), Post synthesis design tasks (Page-765), List of tables (Page-983). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Logic circuits |
| General subdivision | Computer-aided design. |
| 9 (RLIN) | 3116 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Verilog (Computer hardware description language) |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Reference |
| Source of classification or shelving scheme | |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent Location | Current Location | Shelving location | Date acquired | Total Checkouts | Full call number | Barcode | Checked out | Date last seen | Date last checked out | Price effective from | Koha item type | Public note |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 12/12/2016 | 1 | 621.395,CIL | MCS31158 | 07/02/2024 | 03/04/2024 | 03/04/2024 | 12/12/2016 | Book | Almirah No.24, Shelf No.1 |