Verilog HDL: a guide to digital design and synthesis (Record no. 4778)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01454 a2200193 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 8129700921 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | DLC |
| Language of cataloging | DLC |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Palnitkar, Samir. |
| 245 10 - TITLE STATEMENT | |
| Title | Verilog HDL: a guide to digital design and synthesis |
| Remainder of title | a guide to digital design and synthesis |
| Statement of responsibility, etc. | Samir Palnitkar |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Upper Saddle River, NJ : |
| Name of publisher, distributor, etc. | SunSoft Press, |
| Date of publication, distribution, etc. | c2003. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xlii, 490 p. : |
| Other physical details | ill. ; |
| Dimensions | 25 cm. + |
| 500 ## - GENERAL NOTE | |
| General note | "A Prentice Hall title." |
| 500 ## - GENERAL NOTE | |
| General note | "Professional technical reference"--P. [4] cover. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Pt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Verilog (Computer hardware description language) |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Book |
| Call number prefix | 621.392 PAL |
| Source of classification or shelving scheme | |
| Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Total Renewals | Full call number | Barcode | Checked out | Date last seen | Date last checked out | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library (CL) | Central Library (CL) | General Stacks | 09/01/2004 | Allied Book Company | 462.15 | 8 | 2 | 621.392 PAL | SEECS004742 | 05/23/2024 | 04/23/2024 | 04/23/2024 | 01/05/2017 | Book | |||||
| Central Library (CL) | Central Library (CL) | General Stacks | 03/28/2006 | Allied Book Company | 292.50 | 4 | 3 | 621.392 PAL | SEECS007184 | 08/22/2024 | 06/05/2024 | 01/05/2017 | Book | ||||||
| Central Library (CL) | Central Library (CL) | General Stacks | 09/09/2013 | Donation | 0.00 | 11 | 6 | 621.392 PAL | SEECSD00948 | 11/13/2024 | 03/22/2024 | 01/05/2017 | Book |