Low voltage, low power VLSI subsystems / Kiat-Seng Yeo, Kaushik Roy.
Publisher: New York : McGraw-Hill, c2005Description: xxi, 293 p. : ill. ; 23 cmISBN: 007143786XSubject(s): Telecommunication EngineeringDDC classification: 621.395,YEO Online resources: Contributor biographical information | Publisher description | Table of contents
Contents:
Low-Power CMOS VLSI Design (Page-1), Circuit Techniques for Low Power Design (Page-41), Low Voltage Low Power Adders (Page-63), Low Voltage Low Power Multipliers (Page-119), Low Voltage Low Power Read only Memories (Page-147), Low Voltage Low Power Static Random Access Memories (Page-177), Low Voltage Low Power Dynamic Random Access Memories (Page-217), Large Low Power VLSI Sys Design and Applications (Page-257).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Reference
|
Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 621.395,YEO (Browse shelf) | Link to resource | Not for loan | Almirah No.24, Shelf No.1 | MCS32532 |
Total holds: 0
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| 621.395,TRU Design of logic-based intelligent systems / | 621.395,VAN Systematic design of analog IP blocks / | 621.395,WAR Digital design: principles and practices / | 621.395,YEO Low voltage, low power VLSI subsystems / | 621.39732,ALL CMOS analog circuit design / | 621.39732,BAK CMOS : mixed signal circuit design / | 621.39732,WON Nano-CMOS circuit and physical design |
Low-Power CMOS VLSI Design (Page-1), Circuit Techniques for Low Power Design (Page-41), Low Voltage Low Power Adders (Page-63), Low Voltage Low Power Multipliers (Page-119), Low Voltage Low Power Read only Memories (Page-147), Low Voltage Low Power Static Random Access Memories (Page-177), Low Voltage Low Power Dynamic Random Access Memories (Page-217), Large Low Power VLSI Sys Design and Applications (Page-257).
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