Nano-CMOS circuit and physical design Ban P. Wong, Anurag Mittal, Yu Cao, Greg Starr
Publisher: Hoboken, N.J. : John Wiley, c2005Description: xviii, 393 p. : ill. ; 24 cmISBN: 0471466107Subject(s): Telecommunication EngineeringDDC classification: 621.39732,WON Online resources: Contributor biographical information | Publisher description | Table of contents only
Contents:
Nano-CMOS Scaling Problems and Implications (Page-1), Process Technology and Subwavelength Optical Lithography (Page-24), Process Scaling Impact on Design (Page-134), Input/ Output Design (Page-220), Dram (Page-214), Signal Integrity Problems In On-Chip Interconnects (Page-255),Ultralow Power Circuit Design (Page-298), Impact of Physical Design on Manufacturing / Yield and Performance (Page-331), Design for Variability (Page-343).
| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|---|
Reference
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Military College of Signals (MCS) | Military College of Signals (MCS) | Reference | 621.39732,WON (Browse shelf) | Link to resource | Not for loan | Almirah No.24, Shelf No.1 | MCS31507 |
Total holds: 0
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| 621.395,YEO Low voltage, low power VLSI subsystems / | 621.39732,ALL CMOS analog circuit design / | 621.39732,BAK CMOS : mixed signal circuit design / | 621.39732,WON Nano-CMOS circuit and physical design | 621.3981,HIG Performance evaluation of communication networks / | 621.399,HAR Computer and robot vision / | 621.39,COD Coding and signal processing for magnetic recording systems / |
Nano-CMOS Scaling Problems and Implications (Page-1), Process Technology and Subwavelength Optical Lithography (Page-24), Process Scaling Impact on Design (Page-134), Input/ Output Design (Page-220), Dram (Page-214), Signal Integrity Problems In On-Chip Interconnects (Page-255),Ultralow Power Circuit Design (Page-298), Impact of Physical Design on Manufacturing / Yield and Performance (Page-331), Design for Variability (Page-343).
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