Optimizing PowerPC code : programming the PowerPC chip in assembly language / Gary Kacmarcik.
Publisher: Reading, Mass. : Addison-Wesley, c1995Description: viii, 694 p. : ill. ; 23 cmISBN: 0201408392Subject(s): PowerPC microprocessorsDDC classification: 005.265,KAK| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
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Book
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 005.265,KAC (Browse shelf) | Link to resource | Available | Almirah No.5, Shelf No.5 | MCS27008 |
Introduction (Page-1), PowerPC Architecture Overview (Page-9), Instructions Set Overview (Page-27), Branch and Trap Instructions. (Page-35), Load and Store Instructions (Page-57), Integer Instructions (Page-75), Rotate and Shift Instructions (Page-93), Floating Point Instructions (Page-135), System Register Instructions (Page-159), Memory and Caches (Page-173), Pipelining (Page-201), PowerPC 601 Instructions Timing (Page-215), Programming Model (Page-251), Instructions to Optimizing (Page-295), Resource Scheduling (Page-305), More Optimization Techniques (Page-341).
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