Modeling, synthesis, and rapid prototyping with the Verilog HDL / Michael D. Ciletti.

By: Ciletti, Michael DPublisher: Upper Saddle River, N.J. : Prentice Hall, c1999Description: xxii, 727 p. : ill. ; 25 cm. + 2 computer laser optical discs (4 3/4 in.)ISBN: 0139773983Subject(s): Rapid prototyping | Verilog (Computer hardware description language)DDC classification: 621.392,CIL
Contents:
Introduction to Electronic Design Automation (Page-1), Hardware Modeling with the Verilog HDL (Page-22), Event Driven Simulation and Testbenches (Page-63), Logic System Data Types and Operators for Modeling in Verilog HDL (Page-81), User-Defined Primitives (Page-118), Verilog Models of Propagation Delay (Page-131), Behavioral Descriptions in Verilog HDL (Page-159), Synthesis of Combinational Logic (Page-281), Synthesis of Sequential Logic (Page-345), Synthesis of Language Constructs (Page-425), Switch-Level Models in Verilog (Page-495), Design Examples in Verilog (Page-534), Rapid Prototyping with Xilinx FPGAs (Page-610).
Tags from this library: No tags from this library for this title. Log in to add tags.
Item type Current location Home library Collection Shelving location Call number URL Status Notes Date due Barcode Item holds
Book Book Military College of Signals (MCS)
Military College of Signals (MCS)
General Stacks 621.392,CIL (Browse shelf) Link to resource Available Almirha No 124, Shelf No 5 MCS28695
Book Book Military College of Signals (MCS)
Military College of Signals (MCS)
NFIC 621.392 CIL (Browse shelf) Link to resource Available MCS28696
Total holds: 0

Introduction to Electronic Design Automation (Page-1), Hardware Modeling with the Verilog HDL (Page-22), Event Driven Simulation and Testbenches (Page-63), Logic System Data Types and Operators for Modeling in Verilog HDL (Page-81), User-Defined Primitives (Page-118), Verilog Models of Propagation Delay (Page-131), Behavioral Descriptions in Verilog HDL (Page-159), Synthesis of Combinational Logic (Page-281), Synthesis of Sequential Logic (Page-345), Synthesis of Language Constructs (Page-425), Switch-Level Models in Verilog (Page-495), Design Examples in Verilog (Page-534), Rapid Prototyping with Xilinx FPGAs (Page-610).

There are no comments on this title.

to post a comment.
© 2023 Central Library, National University of Sciences and Technology. All Rights Reserved.