VLSI digital signal processing systems : design and implementation / Keshab K. Parhi.
Publisher: New York : Wiley, 1999Description: xx, 784 p. : ill. ; 24 cmISBN: 0471241865 (cloth : alk. paper)Subject(s): Integrated circuits -- Very large scale integrationDDC classification: 621.395,PAR Online resources: Contributor biographical information | Publisher description | Table of Contents| Item type | Current location | Home library | Shelving location | Call number | URL | Status | Notes | Date due | Barcode | Item holds |
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Military College of Signals (MCS) | Military College of Signals (MCS) | General Stacks | 621.395,PAR (Browse shelf) | Link to resource | Available | Almirah No.40, Shelf No.4 | MCS30673 |
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| 621.395,OPE Operational amplifiers : design and applications / | 621.395,PAN VLSI TEchnology / | 621.395,PAN VLSI TEchnology / | 621.395,PAR VLSI digital signal processing systems : design and implementation / | 621.395,PED Circuit design with VHDL / | 621.395,PED Circuit design with VHDL / | 621.395,PIP Linear and interface circuits applications / |
Introduction to Digital Signal Processing Systems (Page-1), Iteration Bound (Page-43), Pipelining and Parallel Processing (Page-63), Retiming (Page-91), Unfolding (Page-119), Folding (Page-149), Systolic Architecture Design (Page-189), Fast Convolution (Page-227), Algorithmic Strength Reduction in Filters and Transforms (Page-255), Pipelined and Parallel Recursive and Adaptive Filters (Page-313), Scaling and Roundoff Noise (Page-377), Digital Lattice Filter Structures (Page-421), Bit-Level Arithmetic Architectures (Page-477), Redundant Arithmetic (Page-529), Numerical Strength Reduction (Page-559), Low Power Design (Page-645), Programmable Digital Signal Processors (Page-695).
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