Design, simulation and testing of an 8-BIT processor using VHDL coding for CPLDs GC Asad Rauf, GC Shahzad Hamid Javaid & GC Shahzaib Alam Khan , PC Malik Qasim Bashir , NC Hasan Shahzad Zaidi
Publisher: Rawalpindi MCS 1999Description: 133 ,pSubject(s): UG Projects | TCC-6DDC classification: 621.382
Contents:
Design methodologies (Page-1-7) Programmable logic devices (Page-8-22) Hardware descriptive languages (Page-23-35) Levels of abstraction (Page-53-62) VHDL for design synthesis (Page-63-71) Processor design (Page-72-90) Our processor (Page-91-122) Software engineering and hardware implementation (Page-123-132)
| Item type | Current location | Home library | Collection | Call number | URL | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|---|
Book
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Military College of Signals (MCS) | Military College of Signals (MCS) | NFIC | 621.382 RAU (Browse shelf) | Link to resource | Available | MCSPTC-20 |
Total holds: 0
Design methodologies (Page-1-7) Programmable logic devices (Page-8-22) Hardware descriptive languages (Page-23-35) Levels of abstraction (Page-53-62) VHDL for design synthesis (Page-63-71) Processor design (Page-72-90) Our processor (Page-91-122) Software engineering and hardware implementation (Page-123-132)
Almirah No.71 Shelf No.1
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