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Development of Verification IP (VIP) for RISC-V based Microprocessors/ Shahid Hussain,

By: Hussain, Shahid Contributor(s): Supervisor: Dr. Rehan Ahmed Material type: Text

TextIslamabad : SEECS, NUST, 2023Description: 74 p. ; 30 cmSubject(s): MS-Electrical EngineeringDDC classification: 200 Online resources: Click here to access online

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Item type	Current location	Home library	Shelving location	Call number	Status	Date due	Barcode	Item holds
Soft Copy	Central Library (CL)	Central Library (CL)	Thesis	200 (Browse shelf)	Available		CL-T-6848

Total holds: 0

Previous	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	Next
Previous	200 DETECTING WEB URL PHISHING: A LIGHTWEIGHT LEXICAL-BASED MACHINE LEARNING METHOD/	200 A Novel Wavelength Shift Keying Technique for the Transmission of Bidirectional Data over FSO Link/	200 An Efficient Phishing URLs Detection Approach Using Supervised Machine Learning/	200 Development of Verification IP (VIP) for RISC-V based Microprocessors/	200 Exploring the rank awareness of Pakistani Khawaja Sara Community: An Interpretative analysis/	200 A Novel Scheme for All-Optical-Regeneration Based on Mach-Zhender Modulator/	200 Trade Credit and Bank Loan Around Financial Crisis: Study on Emerging Markets/	Next

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