Verilog digital system design: RT level synthesis, testbench and verification RT level synthesis, testbench and verification Zainalabedin Navabi.
Series: Publisher: New York : McGraw-Hill, c2006Edition: 2nd edDescription: xvi, 384 p. : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.)ISBN: 0071445641Subject(s): Verilog (Computer hardware description language) | Electronic digital computers -- Computer-aided designDDC classification: 621.392 Online resources: Publisher description | Table of contents only| Item type | Current location | Home library | Collection | Shelving location | Call number | Status | Date due | Barcode | Item holds |
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 NAV (Browse shelf) | Checked out to Sudais Akbar Khan (16101-5364175-7) | 02/09/2025 | SEECS009814 | |
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 NAV (Browse shelf) | Checked out to Aown Aamir (35202-3362949-9) | 03/01/2025 | SEECS007225 | |
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 NAV (Browse shelf) | Checked out to Muhammad Umair Ajmal (33100-5533901-3) | 11/28/2024 | SEECS007226 |
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