TY  - GEN
AU  - Baker,R.Jacob
ED  - Institute of Electrical and Electronics Engineers.
TI  - CMOS circuit design, layout, and simulation
SN  - 047170055X
U1  - 621.38152,BAK 
PY  - 2005///
CY  - New York
PB  - IEEE Press
KW  - Telecommunication Engineering
N1  - Introduction to CMOS Design (Page-1), The Well (Page-31), The Metal Layers (Page-59), The Active and Poly Layers (Page-83),  Resistors, Capacitors, MOSFETs (Page-105), MOSFET Operation (Page-131), CMOS Fabrication by Jeff Jessing (Page-161), Electrical Noise: an overview (Page-213), Models for Analog Design (Page-269), Models for Digital Design (Page-311), The Inverter (Page-331), Static Logic Gates (Page-353), Clocked Circuits (Page-375), Dynamic Logic Gates (Page-397), VLSI Layout Examples (Page-411), Memory Circuits (Page-433), Sensing Using ?S Modulation (Page-483), Special Purpose CMOS Circuits (Page-523),  Digital Phase-Locked Loops (Page-551), Current Mirrors (Page-613), Amplifiers (Page-657), Differential Amplifiers (Page-711), Voltage References (Page-745), Operational Amplifiers I (Page-773), Dynamic Analog Circuits (Page-829), Operational Amplifiers II (Page-863), Nonlinear Analog Circuits (Page-909), Data Converter Fundamentals (Page-931), Data Converter Architectures (Page-965)
UR  - http://www.e-streams.com/es0902/es0902_4363.html
UR  - http://www.loc.gov/catdir/enhancements/fy0620/2004275960-b.html
UR  - http://www.loc.gov/catdir/enhancements/fy0620/2004275960-d.html
UR  - http://www.loc.gov/catdir/enhancements/fy0620/2004275960-t.html
ER  -