Dunn, Ian N. <br/><br/>
A parallel algorithm synthesis procedure for high-performance computer architectures /  
Ian N. Dunn and Gerard G.L. Meyer. 
 - New York :  Kluwer Academic/Plenum Publishers,  c2003. 
 - xi, 108 p. :  ill. ;  24 cm. 
 - Series in computer science .
 - Series in computer science (Kluwer Academic/Plenum Publishers) .
<br/><br/>Introduction (Page-1), Parallel Computing (Page-5),  Parallel Algorithm Synthesis Procedure (Page-13), Review of Matrix Factorization (Page-29), Case Study 1: Parallel Fast Givens QR (Page-41), Case Study 2: Parallel Compact WY QR (Page-75), Case Study 3: Parallel Bidiagonalization (Page-89), Conclusion (Page-101), 
<br/><br/><label>ISBN: </label>0306477432 
<br/><br/><label>LCCN: </label>2003044716 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Computer architecture.<br/>Electronic data processing--Distributed processing.<br/>High performance computing.<br/>Parallel algorithms.<br/>Parallel programming (Computer science)
<br/><br/><label>Dewey Class. No.: </label>004.35,DUN