TY  - GEN
AU  - Wong,Ban P.
AU  - Wong,Ban P.
TI  - Nano-CMOS circuit and physical design
SN  - 0471466107
U1  - 621.39732,WON 
PY  - 2005///
CY  - Hoboken, N.J.
PB  - John Wiley
KW  - Telecommunication Engineering
N1  - Nano-CMOS Scaling Problems and Implications  (Page-1), Process Technology and Subwavelength Optical Lithography  (Page-24), Process Scaling Impact on Design  (Page-134), Input/ Output Design  (Page-220), Dram  (Page-214), Signal Integrity Problems In On-Chip Interconnects  (Page-255),Ultralow Power Circuit Design  (Page-298), Impact of Physical Design on Manufacturing / Yield  and Performance  (Page-331), Design for Variability  (Page-343).
UR  - http://www.loc.gov/catdir/enhancements/fy0616/2004002212-b.html
UR  - http://www.loc.gov/catdir/enhancements/fy0616/2004002212-d.html
UR  - http://www.loc.gov/catdir/toc/ecip0414/2004002212.html
ER  -