TY  - GEN
AU  - Touheed , Hassaan NC    (TCC-9)
TI  - Development of verification and debugging tool for RTL codes in Verilog HDL using co-simulation with C language model
U1  - 621.382 
PY  - 2001///
CY  - Rawalpindi
PB  - MCS,NUST
KW  - UG Projects
KW  - TCC-9
ER  -