TY  - GEN
AU  - Ciletti,Michael D.
TI  - Modeling, synthesis, and rapid prototyping with the Verilog HDL / 
SN  - 0139773983
U1  - 621.392,CIL 
PY  - 1999///
CY  - Upper Saddle River, N.J.
PB  - Prentice Hall
KW  - Rapid prototyping
KW  - Verilog (Computer hardware description language)
N1  - Introduction to Electronic Design Automation (Page-1), Hardware Modeling with the Verilog HDL (Page-22), Event Driven Simulation and Testbenches (Page-63), Logic System Data Types and Operators for Modeling in Verilog HDL (Page-81), User-Defined Primitives (Page-118), Verilog Models of Propagation Delay (Page-131), Behavioral Descriptions in Verilog HDL (Page-159), Synthesis of Combinational Logic (Page-281), Synthesis of Sequential Logic (Page-345), Synthesis of Language Constructs (Page-425), Switch-Level Models in Verilog (Page-495), Design Examples in Verilog (Page-534), Rapid Prototyping with Xilinx FPGAs (Page-610).
ER  -