TY  - GEN
AU  - T.R.Padmanabhan
AU  - Tripura Sundari,B.Bala
TI  - Design through Verilog HDL
SN  - 9812531319
AV  - 621.392 PAD 
U1  - 621.392 PAD 
PY  - 2004///
CY  -  Singapore, Hoboken, NJ
PB  - IEEE Press, Wiley-Interscience
KW  - Verilog (Computer hardware description language)
N1  - 1.introduction to VLSI design(page 1)2.introduction to verilog(page 11)3.language constructs and conventions in verilog (page 31)4.gate level modeling -1(page 47)5.gate level modeling -2 (page 81)6.modeling at data flow level(page 127)7.behavioral modeling -1(page 159)8.behavioral modeling 2(page 219)9.functions,tasks and user defined premitives(page 273)10.switch level modeling(page 305)11.system tasks,functions and compiler directives(page 339)12.queues,PLAS,and FSMS(page 407)
UR  - http://www.loc.gov/catdir/bios/wiley046/2003057671.html
UR  - http://www.loc.gov/catdir/description/wiley039/2003057671.html
UR  - http://www.loc.gov/catdir/toc/wiley032/2003057671.html
ER  -