TY  - GEN
AU  - Sudhakar Yalamanchili
TI  - Introductory VHDL: from simulation to synthesis: from simulation to synthesis
SN  - 8178085585
AV  - 621.392	YAL 
U1  - 621.392 YAL 
PY  - 2001///
CY  - Upper Saddle River, NJ
PB  - Prentice Hall
KW  - VHDL (Computer hardware description language)
ER  -