TY  - GEN
AU  - Brown,Stephen D.
AU  - Vranesic,Zvonko G.
TI  - Fundamentals of digital logic with Verilog design 
SN  - 0072823151
U1  - 621.392BRO 
PY  - 2004///
CY  - New Delhi
PB  - Tata McGraw-Hill
KW  - Logic circuits
KW  - Design and construction
KW  - Data processing
KW  - Verilog (Computer hardware description language)
KW  - Computer-aided design
UR  - http://www.loc.gov/catdir/toc/ecip0716/2007017469.html
ER  -