000 00619nam a22001457a 4500
020 _a9788131501955
082 _a621.395 UYE
100 _aUyemura, John P. (John Paul),
245 _aChip design for submicron VLSI : CMOS layout and simulation
260 _aNew Delhi, India
_bCengage Learning
_c2006
300 _axvi, 411 p.
_bill. ;
_e1 CD-ROM (4 3/4 in.)
500 _aIncludes bibliographical references and index.
650 _a1. Microwind. 2. Metal oxide semiconductors, Complementary --Design and construction. 3. Integrated circuits --Very large scale integration --Design and construction.
942 _cBK
999 _c12448
_d12448