000 01502 a2200301 4500
003 Nust
005 20220726142442.0
010 _a 2003044716
020 _a0306477432
040 _cNust
082 0 0 _a004.35,DUN
100 1 _aDunn, Ian N.
_995242
245 1 2 _aA parallel algorithm synthesis procedure for high-performance computer architectures /
_cIan N. Dunn and Gerard G.L. Meyer.
260 _aNew York :
_bKluwer Academic/Plenum Publishers,
_cc2003.
300 _axi, 108 p. :
_bill. ;
_c24 cm.
490 1 _aSeries in computer science
505 _aIntroduction (Page-1), Parallel Computing (Page-5), Parallel Algorithm Synthesis Procedure (Page-13), Review of Matrix Factorization (Page-29), Case Study 1: Parallel Fast Givens QR (Page-41), Case Study 2: Parallel Compact WY QR (Page-75), Case Study 3: Parallel Bidiagonalization (Page-89), Conclusion (Page-101),
650 0 _aComputer architecture.
650 0 _aElectronic data processing
_xDistributed processing.
_955832
650 0 _aHigh performance computing.
_994234
650 0 _aParallel algorithms.
_936594
650 0 _aParallel programming (Computer science)
_955951
700 1 _aMeyer, Gerard G. L.
_995243
830 0 _aSeries in computer science (Kluwer Academic/Plenum Publishers)
_995244
856 4 1 _3Publisher description
_uhttp://www.loc.gov/catdir/enhancements/fy0820/2003044716-d.html
856 4 1 _3Table of contents
_uhttp://www.loc.gov/catdir/toc/fy042/2003044716.html
942 _2ddc
_cBK
_k004.35,DUN
999 _c176801
_d176801