000			02377nam a22001817a 4500
003			NUST
005			20240923133324.0
082			_a621.382,TAH
100			_aTahir, Shariq Ijlal _9125986
245			_aFPGA Based Polyphase Channelizer / _cNC Shariq Ijlal Tahir, NC Syed Ali Haider Gardazi, NC Muhammad Saim Mushtaq, ASC Muhammad Kashif.
260			_aMCS, NUST _bRawalpindi _c2024
300			_a111 p
505			_aChannelizers are widely used in modern digital communication systems. Advanced uniform multi-rate channelization has been theoretically proved to be capable of reducing the computational load, with a better performance. Therefore, in this thesis, we implement these designs on a FPGA board for the sake of the comprehensive evaluation of resource usage, performance, and frequency response. The uniform filter banks are one of the most essential units in channelization. The Generalized Discrete Fourier Transform Modulated Filter Bank (GDFT-FB), as an important variant of basic a DFT-FB, has been implemented in FPGA and demonstrated with a better computational saving rather than traditional schemes. Moreover, the oversampling version is demonstrated to have a better frequency response with an acceptable number of extra resources. Therefore, FPGA platform along with MATLAB will be used in order to achieve better performance and hardware efficiency. Field Programmable Gate Arrays (FPGAs) are being widely used in a variety of embedded applications. Due to their programmable features, FPGAs are the perfect choice for various hardware-based systems. In many of the competing types of FPGAs, the dominant types are Static Random-Access Memory (SRAM) based which can be reprogrammed at any stage of execution of a job. On the other hand, a polyphase channelizer is a type of channelizer that uses polyphase filtering to filter, downsample, and down-convert simultaneously. This project will demonstrate the FPGA based Polyphase channelizer structure that implements a resource efficient multichannel digital transmitter or receiver for a set of Frequency Division Multiplexed (FDM) channels that exist in a single sampled data stream. Xilinx ISE / Vivado design Suites will be used to implement proposed design.
650			_aUG EE Project _9118090
651			_aBEE-57 _9125983
700			_aSupervisor Dr. Zeeshan Zahid _9118097
942			_2ddc _cPR
999			_c611709 _d611709