Verilog HDL: a guide to digital design and synthesis a guide to digital design and synthesis Samir Palnitkar
Publisher: Upper Saddle River, NJ : SunSoft Press, c2003Edition: 2nd edDescription: xlii, 490 p. : ill. ; 25 cm. +ISBN: 8129700921Subject(s): Verilog (Computer hardware description language)DDC classification: 621.392| Item type | Current location | Home library | Collection | Shelving location | Call number | Status | Date due | Barcode | Item holds |
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 PAL (Browse shelf) | Available | SEECSD00948 | ||
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 PAL (Browse shelf) | Checked out to Umar Nadeem (31302-1064880-5) | 03/01/2025 | SEECS007184 | |
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Central Library (CL) | Central Library (CL) | NFIC | General Stacks | 621.392 PAL (Browse shelf) | Checked out to Muhammad Ammar (33101-3816167-1) | 05/23/2024 | SEECS004742 |
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| 621.392 PAL Verilog HDL: a guide to digital design and synthesis | 621.392 PAL Verilog HDL: a guide to digital design and synthesis | 621.392 PAL Verilog HDL: a guide to digital design and synthesis | 621.392 PAL Verilog HDL: a guide to digital design and synthesis | 621.392 PER VHDL : programming by example | 621.392 PER VHDL : programming by example | 621.392 YAL Introductory VHDL: from simulation to synthesis |
"A Prentice Hall title."
"Professional technical reference"--P. [4] cover.
Pt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples.
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